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Error Correction System

IP.com Disclosure Number: IPCOM000093832D
Original Publication Date: 1966-Mar-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Smith, RM: AUTHOR [+2]

Abstract

This circuit enables a nine-track tape system having a single check bit track to have the same error detection and correction capability of a ten-track system having two check bit tracks. This is accomplished by recording two check bits per nominal bit period in the check bit track.

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Error Correction System

This circuit enables a nine-track tape system having a single check bit track to have the same error detection and correction capability of a ten-track system having two check bit tracks. This is accomplished by recording two check bits per nominal bit period in the check bit track.

The eight data bit tracks plus the check bit track are read from read heads and the read signals are applied to detection circuits C and 1...8 via input line 10. The outputs of the detection circuits are applied to error detection and correction logic 12. The output of the check bit track C is applied to conversion circuit 14. The latter comprises two And's 16 and 18 and a one half bit delay circuit 20. Assuming that a bit period of the data bits 1...8 occupies a time period T, then in the check track two check bits C1 and C2 occupy the same period T. Thus, the information in track C is written at twice the frequency of the information written in the data tracks 1... 8.

During the first half of a bit period the first check bit C1 is gated by And 16 via energization of the one half T clock pulse line. The output of And 16 is delayed by one half a bit period by delay 20. At the end of the bit period, the clock pulse line energizes And 18, the output of which provides check bit C2. At this same clock pulse time, the data in the remaining tracks 1...8 is detected and transferred to logic 12. The delayed output of delay 20 insures that check bit C1 is transferred at...