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Serial Storage Arithmetic System

IP.com Disclosure Number: IPCOM000093839D
Original Publication Date: 1966-Mar-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 4 page(s) / 88K

Publishing Venue

IBM

Related People

Gurski, CS: AUTHOR

Abstract

This high-order to low-order arithmetic unit is used in a serial storage arithmetic system. The latter employs delay line DL 5 shown in D for the storage of plurality of numeric words shown in A. Each word in A has a format as shown in B including a sign digit SD in the first digit location in the word, followed by a plurality of numeric digits. Each digit includes a carry flag CF as shown in C, a plurality of standard binary number indicia and a parity bit C.

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Serial Storage Arithmetic System

This high-order to low-order arithmetic unit is used in a serial storage arithmetic system. The latter employs delay line DL 5 shown in D for the storage of plurality of numeric words shown in A. Each word in A has a format as shown in B including a sign digit SD in the first digit location in the word, followed by a plurality of numeric digits. Each digit includes a carry flag CF as shown in C, a plurality of standard binary number indicia and a parity bit C.

In a difference Mode DM, a first numerical word is to be subtracted from a second numerical word. Each word is located at a unique address in DL 5. The addressing mechanism for DL 5 can be standard. In a machine operating according to the principles to be described, it is necessary to determine which number is to be subtracted from the other so as to facilitate the subtraction operation by avoiding a negative result. The initial examination of the signs of both numbers and a sufficient number of digits in the number prevents a negative result and its consequent complimentation problem. Such prevention is by controlling the direction of the subtraction operation in order to obtain a positive sign for the resulting number. In this manner, the high-order digits are examined to see which number is higher than the other. If they are equal, each succeeding lower order digit is examined until a decision is made. If the smaller operand is always subtracted from the larger, then the necessity for performing the tens complement of the result is precluded. In a slow-speed machine, the time saved by avoiding a tens complement operation is significant.

In operation, the addressing mechanism for DL 5 retrieves the sign digit position of the addend word and transfers the digit to A register 6 by a retiming trigger RT 8 and And 10. The retrieved digit is regenerated into DL 5 through a serial adder SA 12. Immediately decode circuit DC 14 determines whether the sign is plus or minus. A minus is indicated by DC 14 generating an enabling signal for application to decode latch DL 16 through gated And 18. The output of DC 14 is also applied to Exclusive-Or 20 by gated And 22. When the highest order digit of the addend word is located, it is regenerated into DL 5 and transferred to B register 24, where it is stored for future use.

Now the addressing mechanism locates the lowest order digit of the augend word, which digit is also a sign digit, and transfers the augend sign digit to register A. Here the augend sign digit is decoded by DC 14. A minus sign causes an enabling signal to be applied to And 22 where it forms the second input signal to 20. Timing signals are applied to And's 18 and 22 and to And 25 so as to simultaneously gate both minus sign signals to Exclusive-Or 20. When the latter has identical signals applied to it, an output enabling signal is generated for application to additional Exclusive-Or's 26 and 28.

Decode circuit DC 29 determines the operat...