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Browse Prior Art Database

Fast Multiply

IP.com Disclosure Number: IPCOM000093922D
Original Publication Date: 1966-Apr-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Swithers, RA: AUTHOR [+2]

Abstract

Dual multiplication circuits make it possible to access a memory twice for each multiplication cycle during iterative multiplication from a list of two operands with accumulation of the products.

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Fast Multiply

Dual multiplication circuits make it possible to access a memory twice for each multiplication cycle during iterative multiplication from a list of two operands with accumulation of the products.

During the initial memory cycle, the first multiplier A1 and first multiplicand B1 are placed in 10 and 11. For half of the multiplication cycle, the multiplication process is preformed normally between 10 and 11 and accumulator 12. At that time, the contents of 10 are transferred to the second multiplicand circuit 14. Also, the contents of 11 are placed in second multiplier circuit 15 and the contents of 12 are transferred into accumulator 16.

Then the next multiplier A2 and multiplicand B2 are obtained from memory and placed in 10 and 11. For the next half multiplication cycle, the first produce A1B1 is completed in 14, 15, and 16 while half of the second product A2B2 is processed in 10, 11 and 12. At the end of the second half multiplier cycle, the contents of 16 are placed in the third accumulator 18 through adder 17. The environment of 10, 11 and 12 is then shifted directly to 14, 15, and 16, respectively, and the third multiplier A3 and multiplicand B3 is obtained from memory for 10 and 11. After all half multiplier cycles are completed, 18 contains the sum of all products A1B1 + A2B2 + A3B3+...+AnBn.

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