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Simplified Clocking Scheme for STR Operation

IP.com Disclosure Number: IPCOM000093932D
Original Publication Date: 1966-Apr-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Oeters, HR: AUTHOR [+3]

Abstract

Synchronization of semiduplex communications between binary serial data transmission devices is provided employing a single clock device at each station for both transmit and receive operations. Synchronization is maintained by using undercounting or overcounting to advance or retard strobing. The device is particularly useful for communication synchronization between a remote terminal and a data multiplexor.

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Simplified Clocking Scheme for STR Operation

Synchronization of semiduplex communications between binary serial data transmission devices is provided employing a single clock device at each station for both transmit and receive operations. Synchronization is maintained by using undercounting or overcounting to advance or retard strobing. The device is particularly useful for communication synchronization between a remote terminal and a data multiplexor.

One terminal always initiates transmission and the other device adjusts its receive clock, recognize sync characters, enter sync mode and enable its transmission. The initiating device when transmitting adjusts its receive clock, recognize sync, enter sync mode and lock its transmitter clock to its receive clock.

Assume that a clock, not shown, produces one revolution of T1... T4 pulses equal to 1/32 of the anticipated data bit period. Line strobing occurs in apparatus, also not shown, at the zero count of main counter which has a thirty-two count capacity. At T2 of a strobe or zero count in 15, the data line is sampled at 10. If sync mode has not been established to set latch 12, presence of a data change or transition sensed by detector 11 during any clock cycle causes an output from And 14 to force a 16 count into 15. Data is strobed from the line into a register, not shown, at the zero count of 15. When idle sync characters are recognized, latch 12 is set deconditioning 14 to block further forcing of 16 counts...