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Time Tag Generator for Variable Sampling Rate Analog to Digital Converter

IP.com Disclosure Number: IPCOM000093934D
Original Publication Date: 1966-Apr-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Anderholm, FR: AUTHOR

Abstract

Each Convert signal on line 3 causes analog-to-digital converter 1 to sample and convert the analog input signal on line 2. Convert signals are generated by a data compression circuit monitoring, for example, the rate of change of the analog signal and producing Convert signals at a rate proportional thereto. Each digital conversion value is entered into segment 15a of buffer register 15 and is transmitted along with a digital time-tag stored in segment 15b through output gate 17 in response to an end of conversion signal on line 4.

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Time Tag Generator for Variable Sampling Rate Analog to Digital Converter

Each Convert signal on line 3 causes analog-to-digital converter 1 to sample and convert the analog input signal on line 2. Convert signals are generated by a data compression circuit monitoring, for example, the rate of change of the analog signal and producing Convert signals at a rate proportional thereto. Each digital conversion value is entered into segment 15a of buffer register 15 and is transmitted along with a digital time-tag stored in segment 15b through output gate 17 in response to an end of conversion signal on line 4.

The time-tag associated with each conversion value is generated by counter 12 and its associated control circuitry. The tag digitally represents the magnitude of the time lapse which has occurred since the beginning of the preceding Convert signal. This information is required in reconstructing the analog input signal from the digital conversion values.

Operation of the tag generating circuit is as follows. Counter 12 advances in response to inputs from fixed-frequency, free-running oscillator 10 for substantially the full interval between each Convert signal. The latter signal triggers single-shot 6 to produce an output 6a which, through Or 8 and Inverter 9, inhibits And 11 and thus stops 12. Output 6a also causes gate 14 to transmit the counter output to segment 15b of 15. The fall of 6a triggers single-shot 7 to produce an output 7a which resets 12 to a value...