Browse Prior Art Database

Synchronous Bi Phase Modem

IP.com Disclosure Number: IPCOM000093941D
Original Publication Date: 1966-Apr-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Skarshinski, L: AUTHOR

Abstract

The circuit shown schematically is for extracting nonreturn-to-zero NRZ binary signals from a bi-phase modulated signal. The bi-phase modulated signal in line 6 of the waveform drawing, enters at point 6 on the schematic drawing and is squared and limited. The waveform shown on line 7 of the waveform diagram at point 7 in the schematic is thus produced. This square waveform corresponds to the transmitted waveform before distortion in line transmission. The amplifier and limiter employs a zero axis crossing detector to effect the squaring.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Synchronous Bi Phase Modem

The circuit shown schematically is for extracting nonreturn-to-zero NRZ binary signals from a bi-phase modulated signal. The bi-phase modulated signal in line 6 of the waveform drawing, enters at point 6 on the schematic drawing and is squared and limited. The waveform shown on line 7 of the waveform diagram at point 7 in the schematic is thus produced. This square waveform corresponds to the transmitted waveform before distortion in line transmission. The amplifier and limiter employs a zero axis crossing detector to effect the squaring.

The waveform in line 7 is delayed by one-bit time to yield the waveform shown in line 8. This waveform when exclusively Ored with the undelayed waveform 7 yields the NRZ data output waveform 9. The data clock 10, recovered from waveform 7, provides the requisite binary sense for the NRZ signals.

In the waveform diagram the original data shown in line 1 consists of the succession of bits 10110100111000. Because of the one-bit delay the first of these bits cannot be detected at the receiver and is thus lost. However, by preceding the data bits with a succession of zeroes followed by a one bit, to phase the receiver to the transmitter, the receipt of the first data bit following the first one is insured.

1

Page 2 of 2

2

[This page contains 1 picture or other non-text object]