Browse Prior Art Database

Serial Counter Incrementor

IP.com Disclosure Number: IPCOM000093942D
Original Publication Date: 1966-Apr-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Maholick, AW: AUTHOR [+2]

Abstract

Incrementing of a serial count field from high-order to low-order is accomplished through circuitry that monitors the state of the lower ordered count before complementing a count bit. A1 through K count field from a recirculating delay line is serially read into a register 11. If the count is not to be incremented, terminal 12 is not raised and tinning pulses T1...TN sequentially enable And's 14...17 to provide an input through Invert 18 into Exclusive-Or 20. Since line 12 is not enabled, the other input for 20 is absent and the original count field gated into 11 is serially read back into the recirculating delay line at 21 and 22.

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Serial Counter Incrementor

Incrementing of a serial count field from high-order to low-order is accomplished through circuitry that monitors the state of the lower ordered count before complementing a count bit. A1 through K count field from a recirculating delay line is serially read into a register 11. If the count is not to be incremented, terminal 12 is not raised and tinning pulses T1...TN sequentially enable And's
14...17 to provide an input through Invert 18 into Exclusive-Or 20. Since line 12 is not enabled, the other input for 20 is absent and the original count field gated into 11 is serially read back into the recirculating delay line at 21 and 22.

A signal at 12 indicates the count is to be incremented and conditions And-Invert circuits 25...28 each of which requires a one in all lower positions to be fully conditioned. Thus a one in 1 through K1 of the count field conditions 25 so that one input exists to 20 at T1. If K is zero, 14 and 25 cause 20 to indicate at 21 that a one is to be written into the delay line. If K is a 1, the output appears at 22 writing a zero in the delay line.

Similar operations occur with respect to 26, 27 and 28.

For illustration, assume 12 is on and the count read from the delay line contains a 1 in the first position, 17 and 28, and all other positions are zero. At T1, neither 25 nor 14 produce an output and the previous zero for K is reproduced into the delay line at 22. The same circumstance occurs for 26 and 15 at TN-2....