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Method for Forming PN Junction Isolated Integrated Semiconductor Devices

IP.com Disclosure Number: IPCOM000094018D
Original Publication Date: 1966-Apr-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Gunther-Mohr, GR: AUTHOR

Abstract

This method isolates semiconductor devices in an integrated semiconductor structure containing a plurality of semiconductor devices.

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Method for Forming PN Junction Isolated Integrated Semiconductor Devices

This method isolates semiconductor devices in an integrated semiconductor structure containing a plurality of semiconductor devices.

In fabricating monolithic or integrated semiconductor device structures, a PN junction isolation technique is customarily used for electrically isolating individual semiconductor devices formed in the integrated structure. In the formation of an isolating PN junction wall around each semiconductor device, this is generally achieved by a diffusion of the desired type of impurity. Such diffusion is into a region about each semiconductor device which reaches a substrate layer of the same type conductivity. Thus electrical isolation of each device upon the application of a negative potential to the isolating semiconductor material is effectively created.

A plurality of semiconductor devices is shown preferably as transistors having collector, base, and emitter regions. The devices are located in a monocrystalline substrate 10 whose conductivity is opposite to the conductivity type of the collector region. This permits, upon the application of a negative potential to substrate 10, the electrical isolation of each device. In order to reduce the width-to-depth ratio of isolation diffusions, a scribed series of lines 12 is formed on the surface of the structure in the areas where the isolation diffusions are to be carried out. The damage created by the scribe lines is ...