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Browse Prior Art Database

Encapsulation for Semiconductor Devices

IP.com Disclosure Number: IPCOM000094021D
Original Publication Date: 1966-Apr-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Gates, HR: AUTHOR [+2]

Abstract

This encapsulation technique for semiconductor devices permits their use in high-voltage applications.

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Encapsulation for Semiconductor Devices

This encapsulation technique for semiconductor devices permits their use in high-voltage applications.

This is an encapsulation for a PIN diode structure which is formed using appropriately doped monocrystalline silicon material. One such method of fabrication is to epitaxially grow intrinsic semiconductor material on an N/+/ type conductivity monocrystalline silicon substrate. A P/+/ diffusion in the surface of the epitaxially grown semiconductor material followed by an additional N/+/ diffusion creates the PIN diode configuration. An added result from the N/+/ diffusion is that a phosphosilicate glass (P(2)O(5) . SiO(2)) is formed on the thermally grown SiO(2) layer.

This P(2)O(5) . SiO(2) layer serves to increase the stability of the device by gettering undesirable impurities. A glass layer preferably consisting of, in mol percent, 38.3% of SiO(2), 49.4% PbO, 6.6% of B(2)O(3) and 5.7% of Al(2)O(3)is deposited on the P(2)O(5) . SiO(2) layer. This composite dielectric layer encapsulation is superior to other encapsulations in that it permits the PIN diode to be used in very high-voltage applications.

Subsequent to the deposition of the glass layer on the P(2)O(5). SiO(2) layer, a number of openings are formed by using a suitable HF acid solution and conventional masking techniques. An aluminum contact metal is deposited or evaporated into the opening into contact with each P/+/ and N/+/ region. This aluminum evaporation is...