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Browse Prior Art Database

Error Feedback Clocking

IP.com Disclosure Number: IPCOM000094053D
Original Publication Date: 1966-May-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 65K

Publishing Venue

IBM

Related People

Harnett, WT: AUTHOR

Abstract

This circuit provides feedback clocking correction to a phase detection system utilizing a variable frequency clock.

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Error Feedback Clocking

This circuit provides feedback clocking correction to a phase detection system utilizing a variable frequency clock.

In a phase encoded data detection system, data is written by changing the phase of a varying waveform. When read, the waveform is compared with a reference clock signal. When the waveform is in phase with the clock, the recorded data is a binary 1. When the data signal is out of phase with the clock, the recorded data is a binary 0. The clock reference in the timing drawing is generated by a variable frequency clock contained within block 10. If the data signal is recorded on a magnetic tape, there are usually speed variations which cause the data to lead or lag the clock signal. Therefore, a feedback arrangement is provided to change the frequency of the variable frequency clock so that it coincides with the frequency of the data signal and is phase locked to the data. The clock and clock lines are compared with the data and data lines in phase detector 12. The 1's line 14 is positive whenever the clock and data levels agree. The 0's line 16 is positive whenever the clock and data lines disagree.

The feedback signal to correct the variable frequency clock is generated by a logical statement of the condition existing between the data line and the clock line. A sample of the phase comparison of data and clock is taken immediately before and immediately after the mid bit period clock transition. In the timing drawing the transition is indicated by downward going arrows for 1's and upward going arrows for 0's. The before x and after y samples 18 and 20 are generated from the variable frequency oscillator at the times shown in the timing drawing.

Samples are compared with the 1's line 14 and the 0's line 16 in a phase sample circuit 22. An output appears on line 24 if the data is lagging and 0's are recorded, or the data is leading and 1's are recorded (x - 1 + y. 0; 1 = ones line, 0 = zeros line). No output occurs if the clock and data are in phase. An output occurs on line 26 when the data is lagging and 0's are recorded, or leading and 1's are recorded (x - 0 + y - 1). No output occurs on line 26 if the data and clock are in phase. The outputs on lines 24 and 26 indicate the phase error. The status of lines 24 and 26 is stored respectively in store 28 and 30 until the end of the bit period. At this time, a data decision is made as to whether the recorded data is a 1 or a 0 during that bit period. The stores 28 and 30 can be capacitors or single-shots.

The output of phase detector 12 also drives an integrator and voltage comparator 15. The integrator and voltage comparator makes a data decision as to whether the recorded...