Browse Prior Art Database

Shared Storage System Priority Control

IP.com Disclosure Number: IPCOM000094054D
Original Publication Date: 1966-May-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Wissick, WP: AUTHOR [+2]

Abstract

Two data processing systems having divergent, basic operating cycle rates, such as 200 nanoseconds and 500 nanoseconds, respectively, can both have access to a single storage device by this priority circuitry. In the upper drawing, lock trigger 1 can be set by Or 2 in response to a select signal from either system A or system B. When set, it indicates that a storage access is being requested by one of the systems, and that the priority circuit is not to be altered for a certain length of time. This time is determined by the particular implementation of the priority control in dependence upon the manner in which it is utilized. The end of the time is defined by the presentation to trigger 1 of a reset lock TCR signal.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Shared Storage System Priority Control

Two data processing systems having divergent, basic operating cycle rates, such as 200 nanoseconds and 500 nanoseconds, respectively, can both have access to a single storage device by this priority circuitry. In the upper drawing, lock trigger 1 can be set by Or 2 in response to a select signal from either system A or system B. When set, it indicates that a storage access is being requested by one of the systems, and that the priority circuit is not to be altered for a certain length of time. This time is determined by the particular implementation of the priority control in dependence upon the manner in which it is utilized. The end of the time is defined by the presentation to trigger 1 of a reset lock TCR signal. Setting of trigger 1 removes an input from And 3 so that the priority trigger 4 cannot be changed from its reset condition in which the system B is given priority, into a set condition in which system A is given priority. Trigger 4 is always returned to the reset condition by a timed reset signal, the timing of which is related to the time required for the storage device to completely respond to a request.

The output of trigger 1 on its set side is applied to two delay units 5 and 6. Their time delay is adjusted in dependence upon the basic timing rate and the distance from the control circuit to the system of system A and system B, respectively. Delays 5 and 6 provide timing signals for operating circuitry in the lower drawing which start the storage and which indicate either acceptance or rejection of the A request by a particular system. Either one of two And's 7 and 8 cause Or 9...