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# Modulo 2 Adder for DTL Shift Register

IP.com Disclosure Number: IPCOM000094056D
Original Publication Date: 1966-May-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 37K

IBM

## Related People

Crutchfield, RC: AUTHOR

## Abstract

The circuitry constitutes one stage of a shift register with additional logic circuits to add, modulo-2, an outside addend to the contents of the stage. The Nand circuit is basic in each stage. For this description, the Nand function is defined as generating a down level output when all the inputs are at up levels and generating an up level output for any other combination of inputs. The binary values 1 and 0 shown are represented by an up level. The shift input is operative to perform the shift when it has an up level. Otherwise the shift input is a down level. An addend binary 1 is represented by an up level. An addend binary 0 is represented by a down level.

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Modulo 2 Adder for DTL Shift Register

The circuitry constitutes one stage of a shift register with additional logic circuits to add, modulo-2, an outside addend to the contents of the stage. The Nand circuit is basic in each stage. For this description, the Nand function is defined as generating a down level output when all the inputs are at up levels and generating an up level output for any other combination of inputs. The binary values 1 and 0 shown are represented by an up level. The shift input is operative to perform the shift when it has an up level. Otherwise the shift input is a down level. An addend binary 1 is represented by an up level. An addend binary 0 is represented by a down level.

Nand's 10 and 11 are cross coupled to form a multivibrator which is the main storage element in the stage of the shift register.

Nand's 12 and 13 are also cross coupled to form a multivibrator which is the intermediate storage element of the stage. Nand's 14 and 15 have their outputs tied together so as to generate the complement of modulo-2 addition of the addend with the output of Nand
10. Nand's 16 and 17 have their outputs tied together to generate the complement of modulo-2 addition of the addend with the output from Nand 11.

To understand the operation, first consider a no-shift condition when the shift signal is at a down level. In this event the 0 and 1 lines into Nand 10 and Nand 11 and out lines of Nand's 12 and 13 are all at an up level. This effectively loc...