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Branching Instruction Look Ahead

IP.com Disclosure Number: IPCOM000094058D
Original Publication Date: 1966-May-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Adler, JG: AUTHOR [+2]

Abstract

This structure largely eliminates a processing delay due to a branching instruction in large-scale data processors. In such processors, it is usual to have a number of instruction buffer registers such as BR I, BR II, and BR III. Into these, instructions are placed for sequential decoding and execution with new instructions being fetched as the old ones are executed. The fetching is done interspersed with other operations in main storage 4. The address from which the next instructions are to be fetched is in instruction counter IC 5. The latter is incremented after each instruction fetch to call for the next fetch from the next sequential storage address. This method has an unavoidable delay when an unconditional instruction branch is to be made.

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Branching Instruction Look Ahead

This structure largely eliminates a processing delay due to a branching instruction in large-scale data processors. In such processors, it is usual to have a number of instruction buffer registers such as BR I, BR II, and BR III. Into these, instructions are placed for sequential decoding and execution with new instructions being fetched as the old ones are executed. The fetching is done interspersed with other operations in main storage 4. The address from which the next instructions are to be fetched is in instruction counter IC 5. The latter is incremented after each instruction fetch to call for the next fetch from the next sequential storage address. This method has an unavoidable delay when an unconditional instruction branch is to be made. That is, when the branch instruction is executed, the succeeding instruction words prefetched and stored in BR I, BR II, and BR III are not to be used. Thus the machine must wait until the instruction at the branch target address is fetched before processing can be resumed.

This time lag can be avoided by using Storage Data Register SD 6 into which each instruction is temporarily stored as it is fetched. Decode unit DC 7 looks at the instruction or, if there is more than one instruction contained in a storage word, at each of the consecutive instructions in SD 6, to determine if it is an unconditional branch instruction. When such an instruction is decoded, DC 7 immediately sets controls into action to transmit from SD 6, to address adder AD 8, the branch target address from the instruction word. As the actual address is usually generated by combining in AD 8 the target address in the instruction with the value stored in one of a group of base registers, the selected one being indicated as GP(n) 9, DC 7 also gates out the value in GP(n) 9, to AD 8, and sets this new address from AD 8 into...