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Browse Prior Art Database

Computer Status Switching

IP.com Disclosure Number: IPCOM000094059D
Original Publication Date: 1966-May-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 34K

Publishing Venue

IBM

Related People

Anderson, DW: AUTHOR

Abstract

On large data processing systems it is often necessary to change from a programming status to a supervisory status, or to return to a program status. It is desirable that this status changing be done with little or no interruption to the cycling of the machine. In such large machines, there is a main storage MS1 which stores the data operands and the instructions of the programs. Insofar as instructions are concerned, Instruction Unit IU 2 transmits to MS 1 the address it its instruction counter IC 3 to call for the next instruction. The instruction, when received, is stored in one of a group of Instruction Buffer Registers BR 4. Instruction Fetch mechanism IF 5 normally responds to the Instruction Decoder ID 6 to cause the address in IC 3 to be sent to MS 1 each time the instruction in a BR 4 is utilized.

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Computer Status Switching

On large data processing systems it is often necessary to change from a programming status to a supervisory status, or to return to a program status. It is desirable that this status changing be done with little or no interruption to the cycling of the machine. In such large machines, there is a main storage MS1 which stores the data operands and the instructions of the programs. Insofar as instructions are concerned, Instruction Unit IU 2 transmits to MS 1 the address it its instruction counter IC 3 to call for the next instruction. The instruction, when received, is stored in one of a group of Instruction Buffer Registers BR 4. Instruction Fetch mechanism IF 5 normally responds to the Instruction Decoder ID 6 to cause the address in IC 3 to be sent to MS 1 each time the instruction in a BR 4 is utilized. IF 5 tries to maintain at least half of the BR's filled with instructions waiting to be decoded in ID 6. When an instruction is decoded, it can be performed in ID 2, or it can be sent to an Execution device E 7 for performance.

E 7 has the hardware to perform the arithmetic and logical instructions transmitted to it. E 7 stores instructions as they are received in one of a group of Operation Stack registers OS 8 for issuance to execution units in the order in which they are received.

When an interrupt 11 is called for or an instruction which requires a change of machine status is decoded and performed by ID 2, the settings of a number of registers of the machine, including IC 3, are to be preserved. This is effected by putting into MS 1 a word known as the old Program Status Word PSW. Thus the program can be resumed from the interrupted point at some later time. Also a new PSW is brought into ID 2 to control future operations. When a change of machine status is called for, the address of the new PSW is generated either from the instruction or by the interrupt m...