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Measuring Jitter in Magnetostrictive Delay Lines

IP.com Disclosure Number: IPCOM000094133D
Original Publication Date: 1966-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Oliver, BL: AUTHOR

Abstract

A method for testing jitter in magnetostrictive delay lines is shown in drawing A. Clock and pattern generator 1 is controlled to produce, at the clock pulse rate, a serial pulse output corresponding to all possible characters in a sixteen-bit character set. The negative pulse sequences are applied to magnetostrictive delay line 2 which is under test and also to lumped variable delay line 3. The output of delay 2 is applied to pulse width standardizer 4. The latter can be a single-shot. Its output is one input of And 5. The output of delay 3 is applied to a second input of And 5. Indicator 6 shows the amount of delay from the input to the output of delay 3. The maximum input to output delay in 3 is one clock pulse width.

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Measuring Jitter in Magnetostrictive Delay Lines

A method for testing jitter in magnetostrictive delay lines is shown in drawing
A. Clock and pattern generator 1 is controlled to produce, at the clock pulse rate, a serial pulse output corresponding to all possible characters in a sixteen-bit character set. The negative pulse sequences are applied to magnetostrictive delay line 2 which is under test and also to lumped variable delay line 3. The output of delay 2 is applied to pulse width standardizer 4. The latter can be a single-shot. Its output is one input of And 5. The output of delay 3 is applied to a second input of And 5. Indicator 6 shows the amount of delay from the input to the output of delay 3. The maximum input to output delay in 3 is one clock pulse width.

In operation, the amount of delay in 3 is varied incrementally from an initial condition X in drawing B to a position Y in which at least one coincidence of the outputs from 3 and 4 occurs for one complete sequence of all possible characters. Each time that the And condition is satisfied, latch and indicator circuit 7 is energized to indicate the coincidence to the operator: Circuit 8 automatically resets latch 7. This position as read from indicator 6 indicates one worst case jitter condition for delay 2. The delay through 3 is then incrementally increased until such time, position Z, as no coincidence between the outputs of 3 and 4 occurs for the entire character set. This position indicates the...