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Field Effect Transistor

IP.com Disclosure Number: IPCOM000094173D
Original Publication Date: 1966-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

DeWitt, D: AUTHOR

Abstract

This field effect transistor arrangement uses the Schottky barrier electrode principle for the gate electrode of a field effect transistor.

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Field Effect Transistor

This field effect transistor arrangement uses the Schottky barrier electrode principle for the gate electrode of a field effect transistor.

An N-type GaAs region is preferably epitaxially grown. The region has a depth of one micron and a conductivity of 2 x 10/15/ impurity atoms per square centimeter with a mobility of 6000 and is formed on a substrate of insulating gallium arsenide.

The ohmic contacts are sintered SnNi. The gate electrode is preferably formed of gold or a composite metal structure of gold, silver, and gold. The gold layer in contact with the semiconductor structure is preferably about 2 microns thick. The width of the conducting channel is approximately .001 cm and the thickness is .0001. The maximum transconductance for such a device is .2 mho/cm. The maximum drain current is .1 amp/cm. The gate bias for pinch-off is
1.6 volts and the typical gate capacitance, in picofarads, is approximately 20 pf/cm. A gain bandwidth product of approximately 10/9/ is achieved for small signals. For large signals, the on-to-off gate voltage swing is from 0 to -1.6 volts.

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