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Extra Metallization Level for Integrated Resistors

IP.com Disclosure Number: IPCOM000094189D
Original Publication Date: 1966-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Glang, R: AUTHOR [+2]

Abstract

In one type of integrated circuit, resistors are deposited in film form on an insulating glass layer. The latter covers the finished semiconductor device level chip. Problems arise both from the small size of the thin film resistors and the size of the semiconductor integrated circuit chip. Integrated circuit chips of 0. 030'' by 0. 030'' having several resistors on them of dimensions of an order of 0.001'' to 0.010'' are used. Resistors of this size can be held to +/- 5 to 10% of the desired value. Therefore, a precision resistor process is contingent upon the possibility of individual resistor adjustment by trimming or other suitable methods after their deposition. The requirement for resistor trimming leads to the problem of contacting individual resistor terminals with microprobes.

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Extra Metallization Level for Integrated Resistors

In one type of integrated circuit, resistors are deposited in film form on an insulating glass layer. The latter covers the finished semiconductor device level chip. Problems arise both from the small size of the thin film resistors and the size of the semiconductor integrated circuit chip. Integrated circuit chips of 0. 030'' by 0. 030'' having several resistors on them of dimensions of an order of
0.001'' to 0.010'' are used. Resistors of this size can be held to +/- 5 to 10% of the desired value. Therefore, a precision resistor process is contingent upon the possibility of individual resistor adjustment by trimming or other suitable methods after their deposition. The requirement for resistor trimming leads to the problem of contacting individual resistor terminals with microprobes.

Precision resistors can be fabricated by depositing resistor and metal conductor films by any conventional technique. Such occurs after the semiconductor device level chip is coated with a layer of glass or other electrical insulating material. Resistors 1 and an initial metal contact pattern 2 are etched from the deposited layers using standard photoresist and etching procedures. Pattern 2 connects every resistor 1 to a peripheral metal contact 3. For example, on a 0.030'' by 0.030'' chip, there is room for ten to twelve test contacts on 0.008'' centers with each contact measuring 0.006 square inches.

The contacts are sufficiently large to accommodate two microprobes and allow for some misregistration during automatic transport from integrated circuit chip to chip. Center-to-center distance and the...