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Slower Data Flow Schemes Utilizing High Speed Delay Lines

IP.com Disclosure Number: IPCOM000094206D
Original Publication Date: 1966-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Langdon, GG: AUTHOR

Abstract

This arrangement uses higher speed serial storage loops in conjunction with slower speed circuits to form unique multipath data flow methods.

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Slower Data Flow Schemes Utilizing High Speed Delay Lines

This arrangement uses higher speed serial storage loops in conjunction with slower speed circuits to form unique multipath data flow methods.

In order to enable reliable operation of a low-speed serial store, in combination with a high-speed serial store, it is necessary for only one digit signal in each successive group, consisting of a predetermined number n of consecutive digit signals fed out from the high-speed store, to be selected and transferred through a given channel to the slow-speed store. This arrangement permits the storing of a digit signal in the slow-speed store to take n times as long as the digit period of the high-speed store. This means that the slow-speed store operates in conjunction with a store operating n times as fast. By a similar, but reverse process, signals derived from the slow-speed store can be read out in direct order and passed into the high-speed store. This is in such a manner that consecutive derived signals occupy an appropriately selected digit period in each successive group of n digit period throughout the high-speed store or stores, then another selected digit period in each successive group through the store or stores and so on.

Drawing A shows a conventional data flow method utilizing separate delay lines for storage. Drawing B is an adaptation of the conventional flow scheme to provide a unique multipath data flow method utilizing a single high-speed delay line, with a resultant savings in hardware. Other multipath data flow methods can also be arranged.

Combination of several data paths into a single high-speed delay line forms a spiral in the delay line. Spirals of unequal length can be formed by first making n and DL, the length of delay line, relatively prirne. This forms a single spiral of n channels because the lowest common denominator of DL and n is 1. This single spiral can be broken to form 2, 3, or up to n spirals. The formation of a multipath, unequal length data flow method is the feature of this arrangement.

In drawing B, the 11 triggers in register A, shifting with bit time transitions from CL20 to CL1, permit a maximum shift right of 10 bits per pass. This is because A data bits...