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# Multiplication Using 2's Complement Numbers

IP.com Disclosure Number: IPCOM000094210D
Original Publication Date: 1966-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 48K

IBM

## Related People

Liu, LY: AUTHOR [+2]

## Abstract

The article "High Speed Arithmetic in Binary Computers" by O. L. MacSorley, published January 1961 in The Proceedings of the IRE, describes a binary multiplication technique. In this, a plurality of multiplier bits is decoded in groups to develop partial products and a final product utilizing multiples of a binary multiplicand or its complements. The same technique can be utilized with positive and negative binary numbers in which the negative numbers are represented in 2's complement form. In other words, the highest order bit position of a binary number is a 0 for positive numbers and a binary 1 for negative numbers. The multiplication technique produces a correct final product if the sign bit of the multiplier is extended one position and utilized for multiplier decoding.

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Multiplication Using 2's Complement Numbers

The article "High Speed Arithmetic in Binary Computers" by O. L. MacSorley, published January 1961 in The Proceedings of the IRE, describes a binary multiplication technique. In this, a plurality of multiplier bits is decoded in groups to develop partial products and a final product utilizing multiples of a binary multiplicand or its complements. The same technique can be utilized with positive and negative binary numbers in which the negative numbers are represented in 2's complement form. In other words, the highest order bit position of a binary number is a 0 for positive numbers and a binary 1 for negative numbers. The multiplication technique produces a correct final product if the sign bit of the multiplier is extended one position and utilized for multiplier decoding. Such also occurs if the sign position of the Multiplicand is extended a number of positions equal to the length of the final product. The multiplicand therefore becomes a number which is the length of the product and the positions to which the sign bit have been extended enter into the addition and subtractions during the development of the final product.

In the drawing, an 8-bit multiplicand, which can be in 2's complement form in positions 8... 15 of register 10, are to be multiplied by and 8-bit multiplier which can be in 2's complement form in register 11 to produce a 16-bit final product from parallel adder 2. In accordance with the mentioned article, the multiplier in register 11 is decoded in four groups +1XC utilizing the sign position S extended one position for the decoding of the final group GP 4. Further in accordance with the article, the sign position S of the multiplicand in register 10 is extended to the left a number of positions equal to the length of the final product.

In this multiplication system, carry-save adder 13 is utilized for simultaneously producing a carry C and sum S signal for each position 0... 15 based on the simultaneous application of corresponding bit positions from all of the multiplicand multiples produced by the decoding of groups GP 1... GP 4 plus one time the complement of the multiplicand 1XC. GP 1... GP 4 gate the multiplicand and its sign extension from register 10 to adder 13 in accordance with the decoding of the groups GP 1... GP 4 of the multiplier in register 11. Adder 13 operates in such a fashion that, for example in position 8, it must produce a carry C and a sum S for position 8 based on position 8 from all groups GP 1... GP 4 taking into account any carry information from lower order bit positions. The representation shows the number of logic levels required in order t...