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Isolated Switching Circuit

IP.com Disclosure Number: IPCOM000094227D
Original Publication Date: 1966-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 36K

Publishing Venue

IBM

Related People

Walton, CA: AUTHOR

Abstract

Common mode voltage frequently present in analog circuits of process control systems is rendered negligible with this low capacitance switching circuit. The circuit also delivers a nonsymmetrical duty cycle wave with DC offset from a transformer.

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Isolated Switching Circuit

Common mode voltage frequently present in analog circuits of process control systems is rendered negligible with this low capacitance switching circuit. The circuit also delivers a nonsymmetrical duty cycle wave with DC offset from a transformer.

Modulator drive voltage applied at terminals 1 and 2 of transformer 10 produces a modulating voltage at secondary terminals 3 and 4. These are in circuit with capacitor 14 and zener diode 16 for switching field effect transistor FET 18.

Analog signals are applied between input terminals 6 and 8, the latter of which can be at actual or floating ground. FET 18 applies the potential at the terminal 6 to terminal 7 or isolates it from 6. Amplifying or other translating stage 20 can be interposed in the circuit if desired and, as shown, an isolating transformer 22 is used if the input circuit is to float completely. The output voltage of transformer 22 is applied to demodulator 24. The demodulated voltage is delivered at output terminals 26 and 28.

A modulator drive voltage wave, as shown at e1-2, passed through a saturating transformer, produces the necessary output voltage wave e3-4. Application of a pulse wave, e'1-2, in a non saturating manner is an alternate way of obtaining the output wave, e3-4. The switching interval between the times t1 and t2, t2 and t3, etc., need not be uniform as is usually the case.

At the time t1 an initial negative pulse is applied to transformer 10. In a short time of the order of one microsecond, transformer 10 reaches saturation and ceases to deliver voltage in the secondary at terminals 3 and 4. During this voltage delivery interval, a negative pulse at terminal 3 is applied to capacitor 14 and diode 16. Current flows through diode 16 in the conventional forward biased diode manner, charging capacitor 14 positive at terminal 5. As the transformer 10 pulse dies out, the voltage on capacitor 14 brings the voltage on the gate of FET 18 to a value equal to the zener voltage of diode 16.

Thus, during an interval from the end of the time t1 to the time t2, there is a positive voltage at terminal 5 with respect to the terminal 4 across diode 16 and applied to the gate electrode of FET 18. This voltage very slowly decays due to back current leakage but it holds FET 18 nonconducting until it drops below the pinch-off value.

At the time t2 a positive voltage pulse of short duration is...