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Complimentary Triggering of Digital Latches

IP.com Disclosure Number: IPCOM000094232D
Original Publication Date: 1966-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Johnson, AR: AUTHOR

Abstract

The DC latch in drawing A can be reliably set by input pulses of short time duration. Reliability is increased by what is equivalent to a pulse stretching technique.

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Complimentary Triggering of Digital Latches

The DC latch in drawing A can be reliably set by input pulses of short time duration. Reliability is increased by what is equivalent to a pulse stretching technique.

The latch includes a pair of logic circuits 1 and 2 suitably cross coupled via diodes 5 and 8. In the normal reset condition of the latch, transistor 3 is on and transistor 6 is off. Positive-going set pulses appearing at input terminal X1 are applied directly to input diode 7 of 2 and in inverted form to input diode 4 of 1 by way of Inverter 9. The latter exhibits an extremely short time delay so that the inverted negative pulse at X2 initiates turnoff of 3 while the positive pulse at X1 initiates turnon of 6.

Drawing G shows the composite signal appearing at X4 produced by the signal at X2, the signal X1 delayed through block 2, broken line drawing E, and the signal X2 delayed through both circuits 1 and 2, broken line drawing F. Even though the original signal appearing at X1 is extremely narrow, and possibly one which can give marginal operation, at best, it is stretched to the width shown in drawing G. Thus reliable operation of the latch is assured.

A bipolar input to the latch is required to achieve the increased reliability. In drawing A the bipolar input is achieved by additional Inverter 9. Drawing B shows an alternative bipolar input utilizing a center-tapped transformer 10. Secondary winding terminals 11 and 12 are adapted for connection to inpu...