Browse Prior Art Database

Delay Line

IP.com Disclosure Number: IPCOM000094265D
Original Publication Date: 1966-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Gillett, JB: AUTHOR

Abstract

The delay line assembly provides signal delays in the region of two nanoseconds. The assembly is made by printed circuit techniques. It consists of a common substrate 1 of a ceramic material which supports two spiral delay lines 3 and 4, one on each side. Ground planes 5 and 6 are provided between substrate 1 and lines 3 and 4. They are insulated from the delay lines by layers 7 and 8 of dielectric material.

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Delay Line

The delay line assembly provides signal delays in the region of two nanoseconds. The assembly is made by printed circuit techniques. It consists of a common substrate 1 of a ceramic material which supports two spiral delay lines 3 and 4, one on each side. Ground planes 5 and 6 are provided between substrate 1 and lines 3 and 4. They are insulated from the delay lines by layers 7 and 8 of dielectric material.

Planes 5 and 6 are connected by common central spigot 9. The spigot provides a common ground termination for lines 3 and 4. Input connections to lines 3 and 4 are made from one surface of the assembly. Tag 10 connects directly to line 3 and tag 11 connects line 4 by connection 12 through the assembly.

Each plane 5 and 6 is of butterfly shape. Each line 3 and 4 exhibits alternate regions of high inductance and capacitance. The ratio of inductance to capacitance along each line is maintained constant. In the drawing the two ground planes 5 and 6 are shown superimposed one above the other. If they are formed angularly displaced by 90 degrees, then coupling between the two delay lines is reduced.

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