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Logic Level Line Scanner

IP.com Disclosure Number: IPCOM000094309D
Original Publication Date: 1966-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Garcia, J: AUTHOR [+2]

Abstract

The matrix arrangement is for the scanning a group of circuits such as communication lines. The 3x3 crosspoint matrix scans nine lines L1.. L9. Each crosspoint, e. g., C13 comprises two diodes D13 and D'13 and one resistor R13. The connection between C13 and L3 is through resistor R'13. Diodes D belonging to a same row are connected to the base of a same transistor, TX1 for the first row. Resistors R belonging to a same column are connected to the emitter of a same transistor, TY3 for the third column. Diodes D' are grounded in order to derive negative noise pulses.

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Logic Level Line Scanner

The matrix arrangement is for the scanning a group of circuits such as communication lines. The 3x3 crosspoint matrix scans nine lines L1.. L9. Each crosspoint, e. g., C13 comprises two diodes D13 and D'13 and one resistor R13. The connection between C13 and L3 is through resistor R'13. Diodes D belonging to a same row are connected to the base of a same transistor, TX1 for the first row. Resistors R belonging to a same column are connected to the emitter of a same transistor, TY3 for the third column. Diodes D' are grounded in order to derive negative noise pulses.

In order to detect the on or off state of a given line, e. g., L3 to which corresponds crosspoint C13, signals are simultaneously applied to leads X1 and Y3. Should line L3 be on, owing to the signal on Y3, transistor TY3 becomes conductive. A current flows through the base of transistor TX1 which is made conductive. The And consisting of diodes d1 and d'1 is enabled. A signal is sent through diode delta 1 which constitutes one of the inputs of an O. Thus the output of transistor T provides a given logic level signal. Should line L3 be off, transistor TY 3 still becomes conductive but, this time, transistor TX1 stays blocked and no signal is issued from transistor T circuit output.

Scanning operation of all lines is obtained by addressing successively the individual lines, and by collecting the corresponding signals at transistor T circuit output.

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