Browse Prior Art Database

Sequential Access Buffer Control

IP.com Disclosure Number: IPCOM000094327D
Original Publication Date: 1966-Sep-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Teo, W: AUTHOR

Abstract

This control provides bookkeeping for a wrap-around memory. In such, the memory addresses are utilized in an endless fashion to write into the memory as needed and to subsequently read from the memory as requested. The control operates upon the principle that whenever the write address catches up to the read address, the memory is full and further write commands are to be inhibited so as not to destroy data in the buffer. Conversely, when the read address catches up to the write address, all storage positions in the memory have been read and it is empty. Thus, a further read address is to be inhibited so as to prevent rereading of previously utilized data.

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Sequential Access Buffer Control

This control provides bookkeeping for a wrap-around memory. In such, the memory addresses are utilized in an endless fashion to write into the memory as needed and to subsequently read from the memory as requested. The control operates upon the principle that whenever the write address catches up to the read address, the memory is full and further write commands are to be inhibited so as not to destroy data in the buffer. Conversely, when the read address catches up to the write address, all storage positions in the memory have been read and it is empty. Thus, a further read address is to be inhibited so as to prevent rereading of previously utilized data.

The control includes a pair of ring counters 10 and 12. These govern the operation of the write and read memory driver circuits 14 so as to write or read, respectively, at the address in memory 16 designated by either counter 10 or 12. A write or read request applied on line 20 or 22 is passed, unless inhibited by a priority control 24, to the corresponding write mode command line 26 or read mode command line 28. At memory cycle time, a timing signal A actuates drivers 14 to operate the memory in accordance with the signal on 26 or 28 and the address then existing in counter 10 or 12.

Immediately after the memory cycle, a timing pulse B is operative to step 10 or 12, depending on whether the command on lines 20 and 22 is a write or read request.

If this stepping of the counter 1...