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Memory Cell with Low Stand By Power

IP.com Disclosure Number: IPCOM000094352D
Original Publication Date: 1966-Sep-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Feth, GC: AUTHOR

Abstract

An NDRO memory cell requiring low stand-by power comprises enhancement-mode, insulated-gate field-effect transistors and utilizes bit complement-coincident selection techniques.

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Memory Cell with Low Stand By Power

An NDRO memory cell requiring low stand-by power comprises enhancement-mode, insulated-gate field-effect transistors and utilizes bit complement-coincident selection techniques.

The memory cell of A includes a basic flipflop arrangement of transistors T1 and T2 having grounded source electrodes s and cross-coupled gate and drain electrodes d and g. Source electrodes of load transistors T3 and T4 connect to drain electrodes d of T1 and T2 at nodes 1 and 2 respectively. Drain and gate electrodes d and g of T3 and T4 connect to write line 5 and bias word line 7, respectively.

Drain and source electrodes d and s of bit selection transistors T5 and T6 connect to bias word line 7 and nodes 1 and 2, respectively. Gate electrodes g of T5 and T6 connect to bit-write 1 drive line 9 and bit-write 0 drive line 11, respectively. Gate electrode g of read transistor T7 connects to node 2. Source and drain electrodes s and d of T7 connect to sense line 13 and read word line 15, respectively.

During quiescent operation, T3 and T4 are conducting so as to maintain flipflop T1-T2 in a stored 0 or stored 1 state. When conducting, T5 and T6 supply current to nodes 1 and 2, respectively, sufficient to determine the state of flipflop T1-T2 only when T3 and T4 are not conducting.

During a write operation, the voltage along line 5 is initially reduced to equalize the voltages at nodes 1 and 2. The coincident energization of either drive line 9 or 11 drives T5 or T6, respectively, into conduction to set flip-flop T1- T2 in a stored 1 or stored 0 state, respectively. T5 and T6 exhibit a low transconductance g so as to determine the effective load and,hence, t...