Browse Prior Art Database

Readout Driver and Level Setter Circuits

IP.com Disclosure Number: IPCOM000094354D
Original Publication Date: 1966-Sep-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Xylander, MP: AUTHOR

Abstract

The drawings show a readout driver and level setting logical circuitry. These facilitate the transfer of information from one storage medium to another within a computer system. Readout driver circuit, drawing A, has a power inverter and two emitter follower stages. Output 15 is coupled to a low-power level setter circuit, drawing B, having a power inverter and two emitter follower stages.

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Readout Driver and Level Setter Circuits

The drawings show a readout driver and level setting logical circuitry. These facilitate the transfer of information from one storage medium to another within a computer system. Readout driver circuit, drawing A, has a power inverter and two emitter follower stages. Output 15 is coupled to a low-power level setter circuit, drawing B, having a power inverter and two emitter follower stages.

In operation, transistor 11 is normally non-conducting and transistor 14 conducts establishing terminal 15 at approximately -12v. When a negative input signal is applied to input terminal 10, transistor 11 conducts. Transistor 14 is rendered non-conducting with diode 21 serving to clamp the voltage of terminal 15 at approximately -4v. When transistor 26 is in its non-conducting state, the base of transistor 28 is approximately -12v.

Since transistor 28 is coupled in an emitter follower configuration, the emitter is also approximately -12v. When transistor 26 goes into its saturated conducting state, the voltage divider arrangement comprising resistors 31 and 32 puts the base of transistor 29 at approximately -4v. The emitter is also at approximately - 4v. During operation the power dissipation of transistors 28 and 29 is relatively low.

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