Browse Prior Art Database

Peak Detector and Average Detector

IP.com Disclosure Number: IPCOM000094355D
Original Publication Date: 1966-Sep-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

Bidwell, AW: AUTHOR [+3]

Abstract

The peak detector in the upper drawing operates in a two-part cycle. During the first part of this cycle, differential amplifier 2 functions to charge capacitor 3 to the peak amplitude of a signal that is received at input terminal 4. During the second part of the cycle, amplifier 2 is controlled to produce a phase encoded, digital output at terminal 14 that signifies the previously detected peak amplitude.

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Peak Detector and Average Detector

The peak detector in the upper drawing operates in a two-part cycle. During the first part of this cycle, differential amplifier 2 functions to charge capacitor 3 to the peak amplitude of a signal that is received at input terminal 4. During the second part of the cycle, amplifier 2 is controlled to produce a phase encoded, digital output at terminal 14 that signifies the previously detected peak amplitude.

The circuit conditions for the two parts of the cycle are established by two transistors 6 and 7. These are connected to be turned on or off according to control signals applied to circuit input terminals 8 and 9. During the first part of the cycle, while capacitor 3 is being charged, transistor 6 is turned off and a resistor 10 connects the upper terminal of amplifier 2 to receive the signal to be detected. Transistor 7 is turned on and cooperates with diode 11 to charge capacitor 3 to the peak voltage that appears at the amplifier 2 output 14. Capacitor 3 is also connected to the lower input terminal of amplifier 2. The negative feedback that this connection provides gives amplifier 2 unity gain. Thus the amplifier 2 output voltage which is applied to capacitor 3 equals the peak voltage of the signal at terminal 4. During this part of the cycle, input terminal 12 is kept at a fixed potential which appears at the lower terminal of capacitor 3.

At the end of the first part of the cycle, the peak voltage appears at output terminal 13. During the second part of the cycle, the circuit produces a phase- encoded digital output on line 14 corresponding in phase to this peak voltage. Transistor 6 is turned on to establish a reference potential, approximately ground, at the upper input terminal of amplifier 2. Resistor 10 isolates the upper terminal of amplifier 2 from terminal 4. Transistor 7 is turned off so that capacitor 3 is in a series circuit between input terminal 12 and the lower terminal of amplifier 2. Thus the voltage at the lower terminal of amplifier 2 is the sum of the capacitor 3 voltage and the voltage applied to terminal 12.

Amplifier 2 is given a high gain such that it operates at one maximum output condition or the opposite maximum output condition. Such is according to whether the voltage at the lower terminal is higher or lower than the reference voltage at the upper terminal. The waveform that is applied to input terminal 12 sweeps through a voltage range such that amplifier 2 switches from one output state to the other at some time during the second part of the cycle. Amplifier 2 switches sooner or later according to the amount of charge capacitor 3 is given during the first part of the cycle. Thus the phase of the change in voltage at output terminal 14 signifies the peak volta...