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Automatic Channel Switching

IP.com Disclosure Number: IPCOM000094371D
Original Publication Date: 1966-Oct-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 4 page(s) / 74K

Publishing Venue

IBM

Related People

Olnowich, HT: AUTHOR

Abstract

Channels 1, 2, and 3 of A provide triple redundant digital information. The information is applied to input terminals In1, In2, and In3 of latches 10, 11, and 12 where it is converted into three redundant input binary signals A1 - A1, A2 b A2, and A3 -A3 respectively. The presence and absence of a pulse in signals A1, A2, and A3 represent a binary 1 and 0 respectively. Signals. 1, A2, and A3 are the Not counterparts of signals A1, A2, and A3 respectively. Logic circuitry includes disagreement detectors 13, 14, and 15 and error correctors 16, 17, and 18 which process the signals. Thus three redundant output binary signals appear at output terminals Out I, Out 2, and Out 3, respectively, which represent the particular bit of digital information from which it is derived.

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Automatic Channel Switching

Channels 1, 2, and 3 of A provide triple redundant digital information. The information is applied to input terminals In1, In2, and In3 of latches 10, 11, and 12 where it is converted into three redundant input binary signals A1 - A1, A2 b A2, and A3 -A3 respectively. The presence and absence of a pulse in signals A1, A2, and A3 represent a binary 1 and 0 respectively. Signals. 1, A2, and A3 are the Not counterparts of signals A1, A2, and A3 respectively. Logic circuitry includes disagreement detectors 13, 14, and 15 and error correctors 16, 17, and 18 which process the signals. Thus three redundant output binary signals appear at output terminals Out I, Out 2, and Out 3, respectively, which represent the particular bit of digital information from which it is derived.

Each detector 13, 14, and 15 monitors an exclusive one of the input signals and detects for disagreement between the monitored input signal and the two others. Detectors 13, 14, and 15 generate in turn binary conditioning signals C1, C2, and C3, respectively, as well as their respective Not counterparts C1, C2, and C3. Each network 16a, 17a, and 18a logically combines the Not counterpart of its associated channel conditioning signal, the Not counterpart of its channel associated input signal, and the conditioning signal generated by another detector Ored with the Not counterpart of its channel input signal. Networks 16a, 17a, and 18a generate signals A1C, A2C, and A3C respectively. These are commonly Ored in each network 16b, 17b, and 18b from which the triple redundant output signal is derived.

If no disagreement is detected between the three redundant input signals being processed, networks 16a, 17a, and 18a simultaneously provide identical output signals A1C, A2C, and A3C respectively. The triple redundant output signal is derived accordingly by the device in response to the three input signals.

If disagreement is detected in one of the redundant input signals, detectors 13, 14, and I5 automatically stop their respective monitoring actions. The device automatically becomes exclusively responsive to a preselected one of the two other input signals which are not at fault and generates the triple redundant output signal in accordance with the selected input signal. Then the device is periodically checked by a diagnostic computer program to determine if the selected signal is at fault. If an error is so detected, an error signal is generated. This signal, by automatic or manual devices not shown, causes the appropriate one of reset signals M1, M2, and M3 which are associated with detectors 14, 15, and I3, respectively, to be temporarily actuated. The device is thus made responsive to the last or third remaining input signal which is not at fault. Under these latter circumstances, the device continues to generate the triple redundant output signal. The device is now responsive to the last selected input signal in which the device is again pe...