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# Temperature Compensation for Sample and Hold Circuit

IP.com Disclosure Number: IPCOM000094379D
Original Publication Date: 1966-Oct-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 37K

IBM

## Related People

Benson, AB: AUTHOR [+3]

## Abstract

The sample and hold circuit includes buffer amplifier 1, integrating amplifier 2 having holding capacitor C in its feedback path, and diode switch 3. The output of the circuit is connected back to the input by feedback resistor R. When a positive sample signal is applied to 3, C charges until the voltage at the output equals the voltage at the input. When the sample signal goes negative, 3 is reverse biased and the level of the output is held by C, regardless of any changes which occur at the input.

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Temperature Compensation for Sample and Hold Circuit

The sample and hold circuit includes buffer amplifier 1, integrating amplifier 2 having holding capacitor C in its feedback path, and diode switch 3. The output of the circuit is connected back to the input by feedback resistor R. When a positive sample signal is applied to 3, C charges until the voltage at the output equals the voltage at the input. When the sample signal goes negative, 3 is reverse biased and the level of the output is held by C, regardless of any changes which occur at the input.

The network including thermistor T1 and potentiometers P1 and P2 provides a temperature compensated zero offset control for 1. T1 provides a voltage at node A which is a linear function of temperature. To calibrate the network for a range of from 0 degrees C to 60 degrees C, the circuit is placed in a controlled temperature environment. This is maintained at 10 degrees C and the input and output terminals are clamped to ground potential. Under these conditions, A is also at ground and the setting of P1 has no effect on the output of 1. P2 is then adjusted until the output of 1 is exactly zero. This corrects the unavoidable imbalance in the base current requirements of the input transistors of 1. Next, the temperature is raised to 55 degrees C and the output of 1 is again zeroed, this time by adjusting P1. This completes the zero offset calibration.

The network including potentiometers P3 and P4 is provided for elimi...