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Logic Delay Line

IP.com Disclosure Number: IPCOM000094383D
Original Publication Date: 1966-Oct-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Kara, B: AUTHOR

Abstract

In order to delay a pulse by a time greater than the pulse width W, a logic delay line is used. The delay line comprises a pair of parallel single-shots of a delay time T and an output circuit responsive to the trailing edge of each single-shot output. One single-shot is fired by the leading edge of the input pulse. The other, by means of inverters, is fired by the trailing edge of the input pulse. Thus the separation of the trailing edges of the single-shots is equal to the input pulse width. Consequently, the output pulse width is equal to the input pulse width and the delay is the delay time T of the single-shots.

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Logic Delay Line

In order to delay a pulse by a time greater than the pulse width W, a logic delay line is used. The delay line comprises a pair of parallel single-shots of a delay time T and an output circuit responsive to the trailing edge of each single- shot output. One single-shot is fired by the leading edge of the input pulse. The other, by means of inverters, is fired by the trailing edge of the input pulse. Thus the separation of the trailing edges of the single-shots is equal to the input pulse width. Consequently, the output pulse width is equal to the input pulse width and the delay is the delay time T of the single-shots.

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