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Nonsequential Timing Control Apparatus

IP.com Disclosure Number: IPCOM000094426D
Original Publication Date: 1965-Jan-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Busch, DF: AUTHOR [+2]

Abstract

With this apparatus, control may be transferred from any stage to any other stage of a machine (such as a Central Processing Unit CPU) having a plurality of stages or phases.

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Nonsequential Timing Control Apparatus

With this apparatus, control may be transferred from any stage to any other stage of a machine (such as a Central Processing Unit CPU) having a plurality of stages or phases.

Down-level timing pulses TP1 are applied periodically via inverter 1 simultaneously to all stages A, B... N via line 2. Each stage controls operation for a corresponding machine phase. No change to another machine phase occurs unless and until an Early Latch EL of a selectable stage A, B... N is preconditioned on. Such action permits the setting of the Later Latch LL of that stage on by the next succeeding TP1. LL of the selected stage then controls CPU operation until another stage is preconditioned and selected.

For example, assume stage A is on and that all other stages B... N are off. With A on, its EL is off and its LL is on. To set B and reset A, line 3 is brought down by a not set B (SET B) pulse. This turns on EL in B via Inverter 4, And 5 and Or inverter 6, latching back via a branch of line 3. Meanwhile, SET B pulse causes Or inverter 7 to bring up line 8. With EL of B latched, line 10 is up. Hence, on the next TP1 pulse, And 9 is satisfied by lines 2, 8 and 10, bringing line 11 up. LL of B is now turned on via Or inverter 12, And 13 and Or inverter 14, latching back via line 15 to And 16. Simultaneously LL of A is reset because without a SET A pulse and, with EL of A off, fine 17 is up. Hence at TPl time, And 18 is satisfied by fines 17, 8 an...