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Counter Employing Tristable State Circuits

IP.com Disclosure Number: IPCOM000094427D
Original Publication Date: 1965-Jan-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Dieffenderfer, JW: AUTHOR

Abstract

The circuit shows the first two stages of a binary counter which employs stage circuits having three stable information representing states. Each tristable stage circuit has three output lines which are energized two at a time. Each has the characteristic that, when passing from any one of its three stable states to any other, one of the three outputs must remain unchanged while the other two change.

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Counter Employing Tristable State Circuits

The circuit shows the first two stages of a binary counter which employs stage circuits having three stable information representing states. Each tristable stage circuit has three output lines which are energized two at a time. Each has the characteristic that, when passing from any one of its three stable states to any other, one of the three outputs must remain unchanged while the other two change.

The counter is driven by a four phase clock, the phases of which are denominated W, X, Y, and Z as shown. The State Diagrams indicate the operation of the first and second stages of the counter in response to the clock pulses.

This counter employs fewer components than conventional binary counters using triggers or latches. Because of the characteristic that one output of each stage circuit must remain in the on state while the circuit changes state, sliver or race conditions are avoided.

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