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Reentrant Analog to Digital Converter

IP.com Disclosure Number: IPCOM000094433D
Original Publication Date: 1965-Jan-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Gorbatenko, G: AUTHOR [+4]

Abstract

Sample and hold amplifier 10 samples the instantaneous value of analog input signal Ei and holds it for presentation to switch 11. Switch 11 closes to apply the input voltage in parallel to a bank of comparison circuits 20. Each circuit in 20 fires when the voltage presented to it exceeds a predetermined threshold level. Circuits 0... 9 have threshold levels of 0 to 9 volts, respectively. Each produces an output voltage level corresponding to its threshold level. Circuit 19 selects the highest output voltage of the activated comparison circuits and presents it to coding circuit 21. This converts the value of this voltage to a binary number For example if circuits 0 through 5 are activated circuit 21 receives an input signal of 5 volts and generates output signals on lines 1 and 4.

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Reentrant Analog to Digital Converter

Sample and hold amplifier 10 samples the instantaneous value of analog input signal Ei and holds it for presentation to switch 11. Switch 11 closes to apply the input voltage in parallel to a bank of comparison circuits 20. Each circuit in 20 fires when the voltage presented to it exceeds a predetermined threshold level. Circuits 0... 9 have threshold levels of 0 to 9 volts, respectively.

Each produces an output voltage level corresponding to its threshold level. Circuit 19 selects the highest output voltage of the activated comparison circuits and presents it to coding circuit 21. This converts the value of this voltage to a binary number For example if circuits 0 through 5 are activated circuit 21 receives an input signal of 5 volts and generates output signals on lines 1 and
4.

This binary output represents the first, i. e., most significant, decimal conversion digit and is sent via lines 27 to output register 25 for storage. The output of circuit 19 is also presented via line 22 to the minus input of differential amplifier 28 having a gain of ten. The plus input of 28 receives the original input signal through switch 11. The amplified output of 28 is stored by sample and hold amplifier 16. Now, switch 11 opens and switch 12 closes. This causes 20 to receive a new input value, beginning the second digit conversion cycle. At the end of the second cycle, the new amplifier differential voltage is stored by sample and hold amplifier 17. Now, switch 12 opens and switch 13 closes, initiating a third conversion cycle.

The original analog input signal ceases to become an input to the system at the end of the first digit conversion cycle when 11 opens. Because of this loss of the original input reference voltage, subsequent inputs to 20 may be slightly off due to slight inaccuracies in the operation of amplifiers 16 and 17 and switches 12 and 13. Due to the cumulative effect of such errors over a plurality of conversion cycles, the last one or two output digits are very likely to be erroneous. To correct for this, the final output digit, in this example the fourth, is generated. This is effected by comparing the analog equivalent of the digital number generated d...