Browse Prior Art Database

Address Arrangement for Expandable Modular Storage

IP.com Disclosure Number: IPCOM000094446D
Original Publication Date: 1965-Jan-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Carnevale, RJ: AUTHOR

Abstract

This addressing arrangement permits storage capacity to be expanded on a modular basis without increasing selection time or requiring special electronics.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Address Arrangement for Expandable Modular Storage

This addressing arrangement permits storage capacity to be expanded on a modular basis without increasing selection time or requiring special electronics.

Modules X and Y have identical memory address registers MAR, address decode circuits, storage inhibit circuits and clocks. An address bus is connected in parallel via an inverter I to And 2 and also directly to And 3.

If the address is less than the capacity of one module, e. g., below 32K, line 1 is down. Hence, either a Read Call pulse or a Write Call pulse, as the case may be, is transmitted via Or 4 to cause And 2 to activate the clock in X to decode the address in 0-32K storage. However, if the address is between 32K and 64K, line 1 is up. Hence, the output from Or 4 together with line 1 causes And 3 to activate the clock in Y to decode the address in the 32K-64K storage.

Once either clock is started, it runs for a complete read or write cycle, as the case may be. During reading, the selective output from either the X or Y storage is transmitted to a common data register via Or 5. Thus, X or Y is selectively addressed according to whether line 1 is down or up, respectively.

1

Page 2 of 2

2

[This page contains 4 pictures or other non-text objects]