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Pulse Counting Flip Flop

IP.com Disclosure Number: IPCOM000094447D
Original Publication Date: 1965-Jan-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Warren, RA: AUTHOR

Abstract

This circuit utilizes silicon controlled rectifiers for noise discrimination and for preventing oscillation in a saturating transformer oscillator to provide a pulse counting flip-flop.

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Pulse Counting Flip Flop

This circuit utilizes silicon controlled rectifiers for noise discrimination and for preventing oscillation in a saturating transformer oscillator to provide a pulse counting flip-flop.

An input pulse is applied to the control electrodes of both silicon controlled rectifiers, SCR 1 and SCR 2. If the pulse is of sufficient amplitude and duration, it causes both to conduct. Current through resistor network R1 and R2 tends to turn both transistors Q1 and Q2 on. The windings W1 and W2 in the collector circuits of Q1 and Q2 are poled in opposition so that, depending upon the initial saturation flux state of the core, only one winding is effective to switch flux. Windings W3 and W4 are poled regeneratively so that the transistor which provides switching current is held in conduction. The other transistor is back biased and its associated rectifier is reset. For example, if Q1 turns on, SCR 1 is locked on and current flows through Q1 until T1 saturates. After saturation is reached, Q1 turns off and resets SCR 1 preventing oscillation.

This circuit can be used as a single-stage frequency divider or, if used in cascade, as a multiple stage frequency divider. This application is especially useful where the circuit is required to operate over wide temperature and power supply variations. Due to the constant volt-second area of the output waveform of a saturating transformer oscillator, the circuit can also be utilized to provide a regulated voltage...