Browse Prior Art Database

Delay Line Read Only Memory

IP.com Disclosure Number: IPCOM000094464D
Original Publication Date: 1965-Feb-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Fletcher, RW: AUTHOR [+2]

Abstract

Miniature delay line elements coupling the word lines to the sense lines of a matrix provide an effective read-only memory with virtually no signal attenuation.

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Delay Line Read Only Memory

Miniature delay line elements coupling the word lines to the sense lines of a matrix provide an effective read-only memory with virtually no signal attenuation.

The delay line read-only memory is of the broken bit type. Each intersection of word line (column conductors) and sense line (row conductors) is provided with a miniature delay line coupled across the intersection. If all delay lines are permitted to remain intact, the matrix provides all 1 value signals on each of the sense lines whenever any one of the word lines is energized with a selection current. Selected intersections are provided with 0 values simply by breaking the connection of the delay line at that intersection.

The nature of the delay line is to provide a delay of one unit with a minimum of attenuation. The output circuits thus can be ordinary logic circuits instead of amplifiers. The selected word output is delayed exactly one unit. There is a sneak path shown by the broken line for word 2. This extends from the energized selected word line, through a delay line at a 1 intersection, along a sense line, through a second delay line at a second 1 intersection on the same sense line, along an unselected word line, through a third delay line at a third 1 intersection on the unselected word line to a sense line for an error signal. The error signal, however, is delayed at least three delay units and is eliminated by strobing the sense output.

Coupling the read-only mem...