Browse Prior Art Database

Data Processing System Clock Control

IP.com Disclosure Number: IPCOM000094480D
Original Publication Date: 1965-Feb-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Pitkowsky, S: AUTHOR [+3]

Abstract

Main storage units of varying speeds can be attached to a central processing unit (CPU) of a data processing system while maintaining a single, common CPU arrangement. The only limitation to the CPU arrangement is to provide a CPU which operates with a storage unit with the fastest anticipated access time. Slower access storage units are made to appear the same to the CPU as the fastest unit. This is effected by blocking CPU clock pulses to account for the difference in access time. By controlling the gating of CPU clock pulses, differences in access and regeneration time of various storage units as well as the busy status of a storage unit shared, with other devices, can be accounted for.

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Data Processing System Clock Control

Main storage units of varying speeds can be attached to a central processing unit (CPU) of a data processing system while maintaining a single, common CPU arrangement. The only limitation to the CPU arrangement is to provide a CPU which operates with a storage unit with the fastest anticipated access time. Slower access storage units are made to appear the same to the CPU as the fastest unit. This is effected by blocking CPU clock pulses to account for the difference in access time. By controlling the gating of CPU clock pulses, differences in access and regeneration time of various storage units as well as the busy status of a storage unit shared, with other devices, can be accounted for.

It is assumed that the circuit shown operates in a CPU in which the fastest storage unit provides data to be sampled on the fourth CPU clock pulse after the cycle which initiates a storage fetch on line 1. It is also assumed that all storage units which are attached to the CPU provide a positive advance signal on line 2 at least one CPU clock pulse prior to the time data can be accepted by the CPU. CPU clock pulses are generated from And 3 which receives a square wave oscillator output and is enabled by the off condition of trigger 4 through inverter 5.

Trigger 4 is turned on to block CPU clock pulses from either And 6 or And 7 through Or 8. Trigger 4 is turned off to permit the generation of CPU clock pulses through And 9. This is enabled by the on condition of trigger 4, the application of the advance signal from line 2, and an oscillator pulse.

With the application of a square wave oscillator input at line 11 and a signal on line 1 initiating a storage fetch, And 12 is enabled. Such action initiates the on-off sequencing of a series of triggers 13... 18. Triggers 13, 15 and 17 are turned on and then off by the positive half of the CPU oscillator waveform. Triggers 14, 16 and 18 are turned on and off by the second half of a CPU oscillator cycle through inverter 10. As a r...