Browse Prior Art Database

Data Synchronized Clock

IP.com Disclosure Number: IPCOM000094496D
Original Publication Date: 1965-Feb-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Provazek, LD: AUTHOR [+2]

Abstract

This clock circuit operates in a start-stop mode. It is frequency controlled with an error voltage generated by comparing the phase of its output with that of the incoming binary data. The circuit requires a start-of-message indication, i. e., the subcarrier-on signal.

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Data Synchronized Clock

This clock circuit operates in a start-stop mode. It is frequency controlled with an error voltage generated by comparing the phase of its output with that of the incoming binary data. The circuit requires a start-of-message indication, i. e., the subcarrier-on signal.

Between messages, the subcarrier-on signal is off. This causes flip-flops (FF's) 1 and 2 to reset. FF 1 clamps multivibrator 3 off and no clock pulses are produced. FF 2 controls Adder-Integrator (A1) 4 so that its output, i. e., bias for MV 3, is at a known level between messages. This bias insures that MV 4 starts at a nominal frequency at the beginning of a message.

When the subcarrier-on signal goes on, the resets are removed from FF's 1 and 2, but the FF's do not change state.

Single-shot (SS) 5 emits a pulse for each transition of the received data. The pulse duration is equal to one half the data bit period. The leading edge of the first pulse, through inverter 6, sets FF 2. The trailing edge of this pulse sets FF 1 which, in turn, gates on MV 3. The first clock pulse is emitted near the middle of the bit period. Throughout the remaining part of the message, the leading edges of the clock pulses are compared in phase with the trailing edge of each pulse from SS 5. If they are not coincident, a control voltage is generated at the output of AI 4 which causes the clock output to change phase appropriately.

The control voltage is generated in the following manner. FF 2 is...