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Inhibited Logic Circuit

IP.com Disclosure Number: IPCOM000094539D
Original Publication Date: 1965-Feb-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Atkins, JB: AUTHOR

Abstract

This logic circuit produces complementary outputs and utilizes collector clamping to provide an inhibit function.

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Inhibited Logic Circuit

This logic circuit produces complementary outputs and utilizes collector clamping to provide an inhibit function.

Logic inputs A and B are applied via diode And 8 to the base circuit of transistor 10. Complementary output transistors 12 and 14 are coupled to the emitter and collector respectively of transistor 10. Transistor 12 is maintained nonconductive and transistor 14 conductive when transistor 10 is nonconductive. Diode 16 is included between the collector of transistor 10 and base of transistor 14 to provide a necessary voltage translation to assure the nonconduction in transistor 14 when transistor 10 is conductive. Transistor 18 is connected in shunt around transistor 10 and acts as an output inhibitor.

Assuming transistor 18 to be nonconductive, simultaneous A and B inputs to And 8 render transistor 10 conductive causing its collector potential to fall. This negative voltage translation renders transistor 14 nonconductive, thus causing its output to rise indicating the function C. Transistor 12 is rendered conductive by the increased emitter potential of transistor 10 with the resultant fall in its collector potential indicating the complemented output (A + B) C.

If the C inhibit input is raised, transistor 18 becomes conductive and unconditionally prevents conduction in transistor 10 (AB + C). Transistors 12 and 14 thereafter remain conductive and nonconductive, respectively, regardless of variations of the A and B inputs.

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