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Cascode Inverter with a Degater

IP.com Disclosure Number: IPCOM000094558D
Original Publication Date: 1965-Mar-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 22K

Publishing Venue

IBM

Related People

Steiner, SA: AUTHOR

Abstract

A properly poled, heterojunction diode is inserted in the base circuit of the normally saturated transistor of a cascode inverter with a degater. This arrangement reduces the switching noise at the output of the inverter.

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Cascode Inverter with a Degater

A properly poled, heterojunction diode is inserted in the base circuit of the normally saturated transistor of a cascode inverter with a degater. This arrangement reduces the switching noise at the output of the inverter.

Normally; transistors T1 and T2 are off and transistor T3 is in saturation. When T1 is gated on, it causes a drop in the potential, V Out, at the output of the inverter. When T2 is gated on, it usually inhibits this drop in V Out by biasing transistor T3 off. However, when T1 and T2 are turned on simultaneously, the collector-base junction of T3 remains on. This is because of the minority carrier charge stored in the base while T1 and T2 are off. Therefore, in this case, current can flow between the positive source +V1 and the bias source +V2 and cause a drop in V Out irrespective of the biasing of T3 by T2.

To prevent this current flow and the resultant drop in V Out, a properly poled, heterojunction diode D is inserted between +V2 and the base of T3. The heterojunction diode is a majority carrier device so that there is no reverse direction current flow through diode D when T1 and T2 are turned on simultaneously.

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