Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Binary Counter Circuits

IP.com Disclosure Number: IPCOM000094563D
Original Publication Date: 1965-Mar-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Eichelberger, EB: AUTHOR [+2]

Abstract

These circuits are for double-rank, i. e., two flip-flop, binary counters. The circuits operate reliably without the use of delay elements or clocking signals. They do not require complementary inputs or an input inverter. They require the use of only four transistors.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 90% of the total text.

Page 1 of 2

Binary Counter Circuits

These circuits are for double-rank, i. e., two flip-flop, binary counters. The circuits operate reliably without the use of delay elements or clocking signals. They do not require complementary inputs or an input inverter. They require the use of only four transistors.

The flip-flop schematic for the binary counter is shown in drawing 1. It differs from the usual double-rank counters in that true flip-flop T requires negative signals S and R, while false flip-flop F requires positive signals S and R. This allows the logic gates feeding the flip-flops to be fed by the input signal designated at X instead of some being fed by X and some being fed by X.

The fact that the X signal feeds all four of the logic gates also eliminates the hazard problem. As long as the delay through a piece of wire is less the delay through a logic gate plus a flip-flop, the circuit operates reliably. For example, let both T and F equal zero. Assume X changes from 0 to 1. This first causes the S input to flip-flop F to change from 0 to 1 causing F also to change from 0 to 1. This, in turn, causes the F signal feeding the S Or to change from 1 to 0.

As long as the X input to the S Or has already changed from 0 to 1, no hazard pulse appears at S. Thus, the only way for this transition to be unreliable is for the delay through the S And and the F flip-flop to be less than the delay from the X input to the S Or. The other three possible transitions are correspondingly...