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Fully Checking a Carry Look Ahead Adder

IP.com Disclosure Number: IPCOM000094570D
Original Publication Date: 1965-Mar-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Hsieh, P: AUTHOR

Abstract

This circuit completely checks a carry look-ahead adder. Circuit 10 generates a usual sum S1 and a function F1. This, when combined in Exclusive Or 12 with the carry C2, produces a carry dependent sum S1' which should be identical to the usual sum S1. A carry-dependent sum adder is described in IBM Technical Disclosure Bulletin, Vol. 5, No. 7, Dec. 1962 at p. 76.

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Fully Checking a Carry Look Ahead Adder

This circuit completely checks a carry look-ahead adder. Circuit 10 generates a usual sum S1 and a function F1. This, when combined in Exclusive Or 12 with the carry C2, produces a carry dependent sum S1' which should be identical to the usual sum S1. A carry-dependent sum adder is described in IBM Technical Disclosure Bulletin, Vol. 5, No. 7, Dec. 1962 at p. 76.

The parity PS of all the carry-dependent sums S1'...S4' is generated by Exclusive Or tree 14. The parity PC of the carries generated by carry generator 16 is determined by Exclusive Or tree 18. The parity equation PC Y PS Y PA Y PB is determined by parity tree 20. The error output E1 of 20 detects all single sum errors and all odd burst carry errors.

All even burst carry errors are detected by Exclusive Oring the usual sum S1 and the carry dependent sum S1' in every other stage. Thus, Exclusive Or 22 determines S1 V S1' and Exclusive Or 22 determines S3 V S3'. The outputs of Exclusive Or's 22 and 24 are Ored together in Or 26, giving the error output E2.

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