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Browse Prior Art Database

Supplemented Parity Checking for a Binary Arithmetic Unit

IP.com Disclosure Number: IPCOM000094571D
Original Publication Date: 1965-Mar-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Anderson, SF: AUTHOR

Abstract

This error checking system for a parallel adder utilizes a parity bit prediction in addition to carry duplication checking.

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Supplemented Parity Checking for a Binary Arithmetic Unit

This error checking system for a parallel adder utilizes a parity bit prediction in addition to carry duplication checking.

The carries are generated by the carry generator. Predicted parities PC2...PC5 are generated by circuits 10, 12, 14, and 16. However, instead of comparing the actual carries C2...C5 with the predicted carries PC2...PC5 in every order, there is a comparison made only in every other order, i.e., PC3 V C3, PC5 V C5. The carry comparison checking supplements the parity checker 18 (PS V PA V PB V PC) to detect those errors which are undetected by parity checking.

With this arrangement it is unnecessary to compare carries in every order.

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