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Latched Carry Save Adder

IP.com Disclosure Number: IPCOM000094574D
Original Publication Date: 1965-Mar-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Earle, J: AUTHOR

Abstract

High-speed multiplication hardware in prior large size computers has utilized a number of carry-save adders, i. e., a fully binary adder for each binary denomination and no interdenomination carry circuits, to generate partial products. The hardware has stored these partial products in latching registers for feeding back to the adder inputs on the next machine cycle. To enable speed-up of the data transmission around such an adder-register loop, this latched carry-save adder (CSA) allows elimination of the logic levels previously required in the register part of the loop.

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Latched Carry Save Adder

High-speed multiplication hardware in prior large size computers has utilized a number of carry-save adders, i. e., a fully binary adder for each binary denomination and no interdenomination carry circuits, to generate partial products. The hardware has stored these partial products in latching registers for feeding back to the adder inputs on the next machine cycle. To enable speed-up of the data transmission around such an adder-register loop, this latched carry- save adder (CSA) allows elimination of the logic levels previously required in the register part of the loop.

As shown in drawing 1, the carry signals from a previous machine cycle are brought in on line 1 and are combined in CSA 4 with two partial products generated on lines 2 and 3 by different multiplier digits. The binary sum and carry digits as they are generated are latched in CSA 4 during the remainder of a machine cycle. On the second half of the same cycle, these sum and carry digits together with the sum digits from the previous cycle, transferred to a set of latches 5 during the first half cycle and now supplied on line 6, are further combined in CSA 7 and are latched during the second half cycle and the first half of the next cycle. The latched sum and carry factors are returned to one CSA 4 input and latch 5 on lines 1 and 8, respectively.

Each latched CSA is composed of the two circuits shown in drawings 2 and
3. For generation and latching of the sum digit, the circuit in drawing 2 is used. This circuit has an upper group of four And's 11... 14, a corresponding second group of four And's 15... 18 and a lower ninth And 19. All And outputs are complemented internally and are inputs to Or 20. This has an upper output 21 representing the sum signal and a lower output 22 representing the sum signal. The three input signals A, B, and C to be added are supplied on input leads 23, 24, and 25 and their complements...