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Reversible Counter

IP.com Disclosure Number: IPCOM000094577D
Original Publication Date: 1965-Mar-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Comer, DT: AUTHOR

Abstract

The reversible, binary-coded decimal counter has circuitry for counting backward by complementing the counter, counting forward and then recomplementing the counter.

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Reversible Counter

The reversible, binary-coded decimal counter has circuitry for counting backward by complementing the counter, counting forward and then recomplementing the counter.

Pulse 10, to be counted in a forward direction, is applied at input 11. Pulse 12 to be subtracted or counted backward, is applied at input 13. The counter has a plurality of cascaded trigger stages T1...T4 which count forward in response to pulses at input 11, transmitted by Or 15 to terminal 16. Input 13 is connected to inverter 20. Circuit 21 differentiates the leading edge of square-wave pulse 12 into short pulse 22. Input 13 is also connected to a second circuit 23 which differentiates the trailing edge of square-wave pulse 12 into short pulse 24.

These short pulses are transmitted by Or 25 and applied to the complementing inputs of all the trigger circuits of the counter. Thus, the first pulse 22 sets the triggers to the complement of the original setting. A second pulse 24 recomplements the counter to normal condition. The circuit further includes delay network 30 which applies the squarewave backward count pulse 12 to input 16 of the counter. Such occurs after the first differentiated pulse 22 causes the triggers to be complemented and before the second pulse 24 recomplements the triggers.

Thus, the first differentiated pulse complements the counter, the delayed square-wave pulse increments the counter, and the second differentiated pulse recomplements the counter. Such oper...