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Parallel I/O Error Detection and Correction

IP.com Disclosure Number: IPCOM000094583D
Original Publication Date: 1965-Mar-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Wolff, CH: AUTHOR

Abstract

This circuitry provides random and burst error detection and single track burst error correction for a parallel system of recording on a magnetic tape unit. The circuit operates with a nine-track tape system, there being eight information tracks plus one parity track P. Data is recorded on a tape unit in the following manner. The eight bits are received from the computer central processing unit CPU and stored temporarily in a read-write register 10. Certain sets of bits are transferred to linear feedback shift registers 12, 14, 16 and 18. Each shift register is shifted once each time an eight-bit character is received at register 10. At the same time, the data from register 10 is written in parallel on the magnetic tape along with a parity bit.

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Parallel I/O Error Detection and Correction

This circuitry provides random and burst error detection and single track burst error correction for a parallel system of recording on a magnetic tape unit. The circuit operates with a nine-track tape system, there being eight information tracks plus one parity track P. Data is recorded on a tape unit in the following manner. The eight bits are received from the computer central processing unit CPU and stored temporarily in a read-write register 10. Certain sets of bits are transferred to linear feedback shift registers 12, 14, 16 and 18. Each shift register is shifted once each time an eight-bit character is received at register 10. At the same time, the data from register 10 is written in parallel on the magnetic tape along with a parity bit.

When all data characters in a record are processed, register 10 is reset and the contents of registers 12 and 14 are written in parallel as an eight-bit check character C1 following the data. The contents of registers 16 and 18 are written as an eight-bit check character C2 following the check character C1. Thus, two check characters C1 and C2 are written following the data. A ninth parity bit is recorded along with C1 and C2 by using a parity generator. The details of the write circuitry and logic for performing these functions are not shown as they can easily be implemented.

During a read operation, the data is read into register 10 and also into registers 12, 14, 16 and 18. These are shifted each time a character is received at register 10. After all the data plus the ch...