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Browse Prior Art Database

Offset Elimination in Double Emitter Switch

IP.com Disclosure Number: IPCOM000094610D
Original Publication Date: 1965-Mar-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Hilsenrath, M: AUTHOR

Abstract

The offset voltage of the double emitter switch is eliminated by this circuit. A low-level signal E applied to input terminals 1 is connected to output transformer 2 by double emitter switches 3 and 4. These are alternately conductive to provide a push-pull signal to winding 5.

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Offset Elimination in Double Emitter Switch

The offset voltage of the double emitter switch is eliminated by this circuit. A low-level signal E applied to input terminals 1 is connected to output transformer 2 by double emitter switches 3 and 4. These are alternately conductive to provide a push-pull signal to winding 5.

The double emitter switches 3 and 4 are driven by oppositely phased high- frequency signals applied to drive terminals 7 and 8, respectively. The small but discrete offset voltage of the switch is, therefore, added to the input signal.

The addition of reversing relays 9 and 10 having SPDT contacts 11 and 12, 13 and 14, respectively, permits the offset voltage of the switch to be reversed at a rate determined by the relay operating frequency. This can be in the range of five cycles per second. Relays 9 and 10 are driven with oppositely phased signals. The timing of pullin and dropout is selected so that there is always a load on the source connected to terminals 1. Thus, with relay 9 energized, the input signal E plus the offset voltage of switch 3 appears across one half of winding 5. With relay 9 deenergized, the signal across the same half of winding 5 is the input signal E less the offset voltage.

When the signal across winding 5 is rectified and filtered, the offset voltage of both double emitter switches is cancelled out.

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