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Binary Adder With Quaternary Lookahead

IP.com Disclosure Number: IPCOM000094636D
Original Publication Date: 1965-Apr-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Wade, RM: AUTHOR

Abstract

This binary adder utilizes a unique configuration of the lookahead carry levels to enable, within the limits of fan-in of the circuitry used, a reduction to the minimum of the number of logic levels required for the carry function. Such reduction in the number of carry logic levels enables a faster addition cycle and thus shortens the time for a central processing unit cycle. (Image Omitted)

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Binary Adder With Quaternary Lookahead

This binary adder utilizes a unique configuration of the lookahead carry levels to enable, within the limits of fan-in of the circuitry used, a reduction to the minimum of the number of logic levels required for the carry function. Such reduction in the number of carry logic levels enables a faster addition cycle and thus shortens the time for a central processing unit cycle.

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