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Modulo 10 and Modulo 11 Self Check Logic

IP.com Disclosure Number: IPCOM000094654D
Original Publication Date: 1965-Apr-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 82K

Publishing Venue

IBM

Related People

Greene, NE: AUTHOR [+2]

Abstract

In a self-checking number system, a check digit is generated and placed in what will become the units position of the self-checking number. The check digit is obtained by multiplying each digit of the number by a multiplying factor and then summing the resultant products. The multiplying factors are determined by assigning a factor of two to the low-order position of the number and then alternating one, two, one, etc. until the high-order position is reached. Nine is subtracted from any product which exceeds nine, i. e., comprises more than one digit. Tens are subtracted from the final sum until the sum results in a number which is less than ten. The ten's complement of this resulting number is the check digit.

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Modulo 10 and Modulo 11 Self Check Logic

In a self-checking number system, a check digit is generated and placed in what will become the units position of the self-checking number. The check digit is obtained by multiplying each digit of the number by a multiplying factor and then summing the resultant products. The multiplying factors are determined by assigning a factor of two to the low-order position of the number and then alternating one, two, one, etc. until the high-order position is reached. Nine is subtracted from any product which exceeds nine, i. e., comprises more than one digit. Tens are subtracted from the final sum until the sum results in a number which is less than ten. The ten's complement of this resulting number is the check digit.

Checks can be made on the validity of the number as it is being entered into a system by repeating the above procedure. Thus, when the check digit is added to the sum of the products, the result should be a multiple of ten, or 0 modulo-10.

The basic timing for the circuit is oscillator 12 which drives bit ring 16. Eleven pulses emanate from ring 16 sequentially. The first pulse steps a digit-add-cycle clock 18 to digit-add cycle 1 (DAC 1). After eleven pulses have been emitted from ring 16, the digit-add-cycle clock is stepped to DAC 2 via the bit 1 pulse. Thus, each digit-add-cycle is comprised of eleven bit pulses.

Add cycles are controlled by add trigger 20. Add cycles vary directly in length according to the value of the digit keyed. For example, an add cycle for a digit 2 is twice as long as the add cycle for a digit 1. The add cycle for a digit 9 is nine times as long as the digit 1 add cycle.

When a start pulse is received at And 22, start trigger 24 is turned on, energizing And's 26. The inputs to And's 26 comprise weighting factors 1... 7. The outputs of And's 26 are combined in Or 28 to turn on multiply trigger 30. The output of trigger 30 energizes And's 32, the inputs of which are controlled by digits 1... 9, received from an input device, for example, a keyboard. The outputs of And's 32 are combined in Or 34 to turn on trigger 20.

This gates the oscillator pulses 12 via And 14 to accumulator 10. If the weighting factor associated with a keyed digit is 1, then the add cycle occurs only once. the weighting factor equals two, then the add cycle occurs twice. For example, if a digit 9 is keyed in and the weighting factor assigned to digit 9 is two, then the add cycle for digit 9 is repeated twice. Thus, eighteen pulses enter accumulator 10, but the resultant number is eight since accumulator 10 resets to zero on the tenth pulse, that is, it counts modulo-10. In addition, where the weighting factor is two and the keyed-in digit is greater than four, one extra pulse is added to the accumulator. This is accomplished by the logic shown within the dotted lines.

The timing diagram shows an example of a digit entry sequence where the digit equals 5 and the weighting factor assigned...