Browse Prior Art Database

Modulo 10 Self Checking Number System

IP.com Disclosure Number: IPCOM000094655D
Original Publication Date: 1965-Apr-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Stahl, WL: AUTHOR [+2]

Abstract

This apparatus generates a self-checking number which contains an added check digit located in the low-order position. The check digit is obtained by multiplying each digit of the number by a weighting factor and then summing the resulting products. Tens are subtracted from the final sum until the result is a number less than ten. The ten's complement of the final number is the check digit.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 62% of the total text.

Page 1 of 3

Modulo 10 Self Checking Number System

This apparatus generates a self-checking number which contains an added check digit located in the low-order position. The check digit is obtained by multiplying each digit of the number by a weighting factor and then summing the resulting products. Tens are subtracted from the final sum until the result is a number less than ten. The ten's complement of the final number is the check digit.

The basic timing is provided by a ring circuit driven from an oscillator. The outputs of the ring circuit are timing pulses RB1...RB30. Every RB 26 pulse drives a second ring which cycles through digit add cycles DAC1...DAC4. Thus, for each digit add cycle there are thirty timing pulses RB 1...RB30.

Digits are entered via a keyboard and are stored in binary-coded decimal latches which generate outputs D1 bit, D2 bit, E4 bit and D8 bit. If any one of the latches is on, digit add cycle 1 turns on add trigger 10 to begin the arithmetic processing of the digit. The arithmetic is performed modulo-15 by the use of binary accumulator 16 with force adding to convert to the modulo-10. The add cycle, which occurs once for each digit entry, consists of four subcycles DAC1...DAC4. DAC1 gates the keyboard digit into the accumulator once per add cycle. DAC2 gates the keyboard digit again to the accumulator when the weighting factor is equal to two, i.e., WF2 is positive. Digit add cycle 3 forces a seven into the accumulator if WF2 is on and the keyboard digit is greater than 4, to convert from modulo-15 of the accumulator to modulo-10. This effectively subtracts nine modulo-10. If the accumulator is greater than nine, digit add cycle 4 forces a six into the accumulator which effectively subtracts ten modulo-10.

The following table illustrates the calculation of the check digit for 64235, mod-10, using modulo-15 arithmetic. The timing diagram also shows this calculation.

Keyboard Accumulator Contents (Mod 15 arithmetic) Digit WF DAC 1 DAC 2 DAC DAC 4

6 2 6 6+6=12 WF=2 3

6>4

12+7=3

4 1 3+4=7 7 7 7

2 2 7+2=9 9+2=11 11 11>9

11+6=1

3 1 1+3=4 4 4 4

5 2 4+5=9 9+5=14 WF=2

574

14+7=5 5

Generator 5+5=10 cycle
Complement of Accumulator 15-10=5
Check Digit = 5

The timing diagram shows an example of the operation of a digit add cycle. The digit chosen is 6 with a weighting factor of two. Digit add cycle 1 commences at RB26. Trigger 10 is turned on at RB28 by the coincidence of weighting factor

1

Page 2 of 3

two (WF2), digit add cycle 1, and an enter command. Since a digit 6 is present at the keyboard, D2 bit and D4 bit lines are energized. RB7 turns on data trigger 12 which i...